The present invention relates to digital latches and latch chains having improved sensitivity.
FIG. 1 shows a conventional digital latch 1 that includes a sample stage 2 with complementary voltage inputs 3, 4, a hold stage 5, and matched transistors 6, 7 having complementary voltage outputs 8, 9. The transistors 6,7 are biased by complementary currents through matched resistors R.
During a sample period, sample stage 2 generates a current through resistors R to produce a voltage difference Vab between nodes A and B responsive to the voltage difference Vinxe2x88x92{overscore (V)}in between input terminals 3 and 4. The values of the voltage difference Vab correspond logical values +1 and 0. During a subsequent hold period, hold stage 5 maintains the current through resistors R so that the voltage difference Vab remains unchanged. The voltages at nodes A and B cause output voltages Vout and {overscore (V)}out at output terminals 8 and 9, respectively. The difference between output voltages Vout and {overscore (V)}out is indicative of the logic value stored during the previous sample period. During the hold period, external digital devices may sample the voltages at terminals 8, 9 to determine the logic value stored in the latch 1.
The sensitivity of a latch to input voltages sets performance limitations on several mixed-signal integrated circuit (IC) applications of the latch. These applications include digital phase detection in clock-data recovery circuits and fiber receivers. Improved circuit performance in such applications may be realized by improving the sensitivity of the latch.
It is therefore desirable to develop a digital latch and latch chain with improved sensitivity to input voltages.
One aspect of the present invention is directed to a latch chain having improved input voltage sensitivity. The chain includes a first latch, an amplifier, and a second latch connected in series. The second latch is a conventional latch. The first latch is modified to have a higher sensitivity and lower output voltage swing than conventional latches. The modified latch includes a pair of matched output transistors that generate output voltages and a pair of matched biasing circuits to bias the bases of the output transistors with bias voltages. A sample stage is connected so as to apply first biasing currents to one of the biasing circuits in response to input voltages applied to the first latch during the sample period. In addition, a hold stage is connected so as to apply second biasing currents to the biasing circuits during a hold period. The sample and hold stages are configured to apply different voltage differences between the bases of the output transistors.